基本解釋[計(jì)算機(jī)科學(xué)技術(shù)]位并行英漢例句雙語(yǔ)例句In this paper, we present a bit plane-parallel architecture for zero tree coding which is suitable for VLSI implementation.提出了比特平面并行處理的零樹(shù)編碼結(jié)構(gòu)。SCSI-1 defined an 8-bit parallel interface with a 5MHz data clock, providing a maximum data transfer rate of 5 megabytes per second (MB/s).SCSI-1 定義了一種具有 5MHz 數(shù)據(jù)時(shí)鐘的 8-bit 并行接口，能提供最高 5 兆字節(jié)每秒（5 MB/s）的數(shù)據(jù)傳輸速率。After the detailed analysis of EBCOT algorithm and pass-parallel coding technique, a dual context window bit-parallel coding method and its architecture for hardware implementation are proposed.通過(guò)研究EBCOT編碼原理和通道并行算法的編碼過(guò)程，提出了雙上下文窗口位并行的EBCOT系數(shù)位建模方法，詳細(xì)說(shuō)明了使用該算法的系數(shù)位建模系統(tǒng)的硬件結(jié)構(gòu)。權(quán)威例句Using Linux-based servers working in parallel, they generate a computer model of how a drill bit must twist and turn to hit one or more formations as much as 9, 000 meters below the sea floor.FORBES: The delicate art of sucking upbit-parallel更多例句詞組短語(yǔ)短語(yǔ)bit plane -parallel and pass-parallel 比特平面與編碼過(guò)程全并行bit -parallel logical instruction 位平行邏輯指令Bit -wise parallel algorithm 逐位并行算法word -serial and bit-parallel 字組串行位并行bit-parallel更多詞組專(zhuān)業(yè)釋義計(jì)算機(jī)科學(xué)技術(shù)位并行All the multiplier architectures proposed in this thesis are bit-parallel finite field multipliers which canimprove the efficiency of cryptosystems significantly.考慮到目前信息安全系統(tǒng)的有效性,本文所提出的有限域乘法器結(jié)構(gòu)均為位并行乘法器。