bit-synchronous

基本解釋

This paper discusses the advantages of PLD (programmable logical device) in designing a digital circuit,and at the same time,discusses how to realize a 6 bit synchronous up/down counter with clear by using PLD GAL16V8.
介紹了PLD器件在設(shè)計(jì)數(shù)字電路時(shí)的優(yōu)越性，同時(shí)敘述了以PLD器件GAL16V8實(shí)現(xiàn)六位可清零、可置數(shù)的同步可逆計(jì)數(shù)器的原理。
Taking PCM/DPSK for example, the effects by Doppler velocity during the course of bit synchronization and demodulation are analyzed.
并以PCM/DPSK信號(hào)為例, 分析了多普勒頻率對(duì)位同步及解調(diào)過(guò)程的影響。
For receiving data correctly , another important problem of TDM system is how to realize bit synchronizing and frame synchronizing .
為了正確的接收數(shù)據(jù),時(shí)分復(fù)用系統(tǒng)需要解決的另一重要技術(shù)就是位同步和幀同步的問(wèn)題。
He bit off a large piece of the apple.
他咬下一大塊蘋(píng)果。
She was a bit queer after her husband deserted her.
她遭丈夫遺棄後精神有點(diǎn)失常。