基本解釋[計算機科學技術]邏輯門級邏輯閘級英漢例句雙語例句Using gate level modeling might not be a good idea for any level of logic design.使用門級建模對于任何邏輯設計都不是一個好的設計。Level restoration pass-transistor logic is proposed for low speed cell while dynamic transmission gate logic for high speed cell.低速單元采用帶有電平恢復的傳輸管邏輯實現(xiàn)，高速單元采用動態(tài)傳輸門邏輯實現(xiàn)。The pre-functional cell of standard buffered FET logic (BFL) adopted by the gate array possesses nine logic functions, two different kinds of driving capabilities, and the level control ability.此門陣列采用的BFL預功能級標準邏輯單元，具有九種組合邏輯功能及兩種不同選擇的驅(qū)動能力，并具有輸出電平調(diào)節(jié)功能。logic gate level更多例句詞組短語短語low level logic gate 低電平邏輯門電路Gate Level logic Design 閘口邏輯設計gate level logic simulation [計]門級邏輯模擬;閘位準邏輯仿真logic gate level更多詞組專業(yè)釋義計算機科學技術邏輯門級邏輯閘級