基本解釋[電子、通信與自動控制技術(shù)]邏輯模擬英漢例句雙語例句This paper presents design and implementation of the simulation module in a logic-level VHDL simulation system.介紹了VHDL邏輯級模擬系統(tǒng)中模擬模塊的設(shè)計和實現(xiàn)。With appropriate tool support, designers could perform execution or simulation and debugging on high-level system models to validate and verify system logic early on.有了適當(dāng)?shù)墓ぞ咧С?，設(shè)計人員可以在高層的系統(tǒng)模型上進行執(zhí)行或模擬，并調(diào)試，從而在早期確認(rèn)并驗證系統(tǒng)邏輯。logic-level simulation更多例句專業(yè)釋義電子、通信與自動控制技術(shù)邏輯模擬