CPPLL

基本解釋

• 電荷泵鎖相環(huán)

同根派生

• CPPLL相關(guān)詞

英漢例句

• And finally, a clock generator based on the 3rd order CPPLL is fully designed with UMC 0.25 CMOS process.
  最後，採(cǎi)用UMC 0.;25 CMOS工藝技術(shù)設(shè)計(jì)了一個(gè)用作時(shí)鍾産生的三堦電荷泵鎖相環(huán)。
• The application of my CPPLL is deserializer in video system, sampling high frequency data by low frequency clock to generate parallel low frequency data output.
  通過(guò)對(duì)時(shí)鍾的頻率和相位的同步，多相位輸出，來(lái)對(duì)高速串行數(shù)據(jù)進(jìn)行解串，輸出低速竝行信號(hào)。
• 4th order CPPLL
  4堦電荷泵鎖相環(huán)

• CPPLL更多例句